A semiconductor memory apparatus includes a main bank configured to combine a first sub bank and a second sub bank. A center bitline sense amplifier array is arranged in a region where the first sub bank meets the second sub bank. A first precharge section is arranged above the first sub bank and a second precharge section is arranged below the second sub bank. The first precharge section precharges local input/output lines of the first sub bank and the second sub bank and the second precharge section precharges the local input/output lines.