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US07664930B2 Add-subtract coprocessor instruction execution on complex number components with saturation and conditioned on main processor condition flags 失效
对具有饱和度的复数分量加减去协处理器指令,并以主处理器条件标志为条件

Add-subtract coprocessor instruction execution on complex number components with saturation and conditioned on main processor condition flags
Abstract:
Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate real components for complex multiplication of first operand complex data and corresponding second operand complex data, a cross multiply and add instruction to generate imaginary components for complex multiplication of the first operand complex data and the corresponding second operand complex data, an add-subtract instruction to add real components of the first operand to imaginary components of the second operand and to subtract real components of the second operand from imaginary components of the first operand, and a subtract-add instruction to subtract the imaginary components of the second operand from the real components of the first operand and to add the real components of the second operand to the imaginary components of the first operand.
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