A controlling circuit for controlling an operating clock of a logic circuit in an electronic device and the method thereof are disclosed. The controlling circuit includes a storage device, a detector, at least one comparator, and a controller. The storage device stores a first threshold value and a first return value. The detector detects a system load of the electronic device to generate a detection value. The comparator compares the detection value with the first threshold value or the first return value. When the detection value decreases to reach the first threshold value, the comparator generates a first indication signal. When the detection value increase to reach the first return value, the comparator generates a second indication signal. The controller enables underclocking of the logic circuit when receiving the first indication signal, and disables underclocking of the logic circuit when receiving the second indication signal.