Invention Grant
- Patent Title: In situ processor margin testing
- Patent Title (中): 原位处理器边缘测试
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Application No.: US11509856Application Date: 2006-08-25
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Publication No.: US07665005B2Publication Date: 2010-02-16
- Inventor: Craig P. Szydlowski
- Applicant: Craig P. Szydlowski
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Thomas R. Lane
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F9/455

Abstract:
Embodiments of apparatuses, methods, and systems for in situ processor margin testing are disclosed. In one embodiment, an apparatus includes virtual machine control logic and operating point control logic. The virtual machine control logic is to transfer control of the apparatus between a virtual machine monitor and a guest. The operating point control logic is to set the operating point of the apparatus in connection with a transfer of control of the apparatus to the virtual machine monitor.
Public/Granted literature
- US20080082881A1 In situ processor margin testing Public/Granted day:2008-04-03
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