Invention Grant
US07666712B2 Design of BEOL patterns to reduce the stresses on structures below chip bondpads
失效
BEOL模式的设计,以减少低于芯片焊盘的结构上的应力
- Patent Title: Design of BEOL patterns to reduce the stresses on structures below chip bondpads
- Patent Title (中): BEOL模式的设计,以减少低于芯片焊盘的结构上的应力
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Application No.: US12133442Application Date: 2008-06-05
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Publication No.: US07666712B2Publication Date: 2010-02-23
- Inventor: Elie Awad , Mariette A. Awad , Kai D. Feng
- Applicant: Elie Awad , Mariette A. Awad , Kai D. Feng
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb I.P. Law Firm, LLC
- Agent Anthony Canale
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A semiconductor structure comprising a substrate including a first layer comprising a first material having a first modulus of elasticity; a first structure comprising a conductor and formed within the substrate, the first structure having an upper surface; and a stress diverting structure proximate the first structure and within the first layer, the stress diverting structure providing a low mechanical stress region at the upper surface of the first structure when a physical load is applied to the first structure, wherein said low mechanical stress region comprises stress values below the stress values in areas not protected by the stress diverting structure. The stress diverting structure comprises a second material having a second modulus of elasticity less than the first modulus of elasticity, the second material selectively formed over the upper surface of the first structure for diverting mechanical stress created by the physical load applied to the first structure.
Public/Granted literature
- US20080233681A1 Design of BEOL Patterns to Reduce the Stresses on Structures Below Chip Bondpads Public/Granted day:2008-09-25
Information query
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