Invention Grant
- Patent Title: Method of forming amorphous source/drain extensions
- Patent Title (中): 形成非晶源极/漏极延伸部分的方法
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Application No.: US11614300Application Date: 2006-12-21
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Publication No.: US07666748B2Publication Date: 2010-02-23
- Inventor: Amitabh Jain
- Applicant: Amitabh Jain
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Rose Alyssa Keagy; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations and depositing amorphous silicon within the recess to from amorphous silicon source/drain extensions. Dopants may be implanted into the amorphous silicon source/drain extensions and the semiconductor wafer may then be annealed.
Public/Granted literature
- US20070099388A1 Source/Drain Extensions Having Highly Activated and Extremely Abrupt Junctions Public/Granted day:2007-05-03
Information query
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