Nanosilicon semiconductor substrate manufacturing method and semiconductor circuit device using nanosilicon semiconductor substrate manufactured by the method

Invention Grant

US07666763B2 Nanosilicon semiconductor substrate manufacturing method and semiconductor circuit device using nanosilicon semiconductor substrate manufactured by the method 有权

Title translation: 纳米硅半导体衬底的制造方法和半导体电路器件采用纳米硅半导体衬底制造的方法

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Patent Title: Nanosilicon semiconductor substrate manufacturing method and semiconductor circuit device using nanosilicon semiconductor substrate manufactured by the method
Patent Title (中): 纳米硅半导体衬底的制造方法和半导体电路器件采用纳米硅半导体衬底制造的方法
Application No.: US12128465

Application Date: 2008-05-28
Publication No.: US07666763B2

Publication Date: 2010-02-23
Inventor: Yukinobu Murao , Akira Kumagai , Yoichiro Numasawa
Applicant: Yukinobu Murao , Akira Kumagai , Yoichiro Numasawa
Applicant Address: JP Kawasaki-shi, Kanagawa-ken
Assignee: Canon Anelva Corporation
Current Assignee: Canon Anelva Corporation
Current Assignee Address: JP Kawasaki-shi, Kanagawa-ken
Agency: Fitzpatrick, Cella, Harper & Scinto
Priority: JP2007-141695 20070529; JP2008-121634 20080507
Main IPC: H01L21/20
IPC: H01L21/20

Nanosilicon semiconductor substrate manufacturing method and semiconductor circuit device using nanosilicon semiconductor substrate manufactured by the method

Abstract:

This invention provides a substrate structure capable of controlling the threshold voltage of a MOS transistor independently of the substrate concentration and easily suppressing a short channel effect caused by reducing the channel length. A first nanosilicon film formed from nanosilicon grains having the same grain size is formed on a silicon oxide film on the surface of a silicon substrate. A silicon nitride film is formed on the first nanosilicon film. Then, a second nanosilicon film having an average grain size different from that of the first nanosilicon film is formed. A semiconductor circuit device is formed on a thus manufactured nanosilicon semiconductor substrate.

Abstract(Chinese):

本发明提供了一种能够独立于衬底浓度来控制MOS晶体管的阈值电压的衬底结构，并且容易抑制由通道长度减小引起的短沟道效应。在硅衬底的表面的氧化硅膜上形成由具有相同粒径的纳米硅粒子形成的第一纳米硅膜。在第一纳米硅膜上形成氮化硅膜。然后，形成平均粒径与第一纳米硅膜不同的第二纳米硅膜。在这样制造的纳米硅半导体衬底上形成半导体电路器件。

Public/Granted literature

US20080296579A1 NANOSILICON SEMICONDUCTOR SUBSTRATE MANUFACTURING METHOD AND SEMICONDUCTOR CIRCUIT DEVICE USING NANOSILICON SEMICONDUCTOR SUBSTRATE MANUFACTURED BY THE METHOD Public/Granted day:2008-12-04

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Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/18	...器件有由周期表Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体，如掺杂材料
H01L21/20	....半导体材料在基片上的沉积，例如外延生长