Invention Grant
- Patent Title: Substrate patterning for multi-gate transistors
- Patent Title (中): 多栅极晶体管的衬底图案化
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Application No.: US11388526Application Date: 2006-03-23
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Publication No.: US07666796B2Publication Date: 2010-02-23
- Inventor: Ibrahim Ban , Uday Shah , Allen B. Gardiner
- Applicant: Ibrahim Ban , Uday Shah , Allen B. Gardiner
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Kenneth A. Nelson
- Main IPC: H01L21/302
- IPC: H01L21/302

Abstract:
Some embodiments of the present invention include apparatuses and methods relating to improved substrate patterning for multi-gate transistors.
Public/Granted literature
- US20070224815A1 Substrate patterning for multi-gate transistors Public/Granted day:2007-09-27
Information query
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