Invention Grant
- Patent Title: Local ESD protection for low-capicitance applications
- Patent Title (中): 本地ESD保护用于低招标申请
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Application No.: US11739801Application Date: 2007-04-25
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Publication No.: US07667243B2Publication Date: 2010-02-23
- Inventor: Charvaka Duvvury , Gianluca Boselli
- Applicant: Charvaka Duvvury , Gianluca Boselli
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Rose Alyssa Keagy; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L23/62
- IPC: H01L23/62
Abstract:
A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad (301) against ESD events, when the I/O pad is located between a power pad (303) and a ground potential pad (305a). A first diode (311) and a second diode (312) are connected in series, the anode (311b) of the series connected to the I/O pad and the cathode (312a) connected to the power pad. A third diode (304) has its anode (304b) tied to the ground pad and its cathode (304a) tied to the I/O pad. A string (320) of at least one diode has its anode (321b) connected to the series between the first and second diode (node 313), isolated from the I/O pad, and its cathode (323a) connected to the ground pad. The string (320) may comprise three or more diodes.
Public/Granted literature
- US20070284666A1 Local ESD Protection for Low-Capicitance Applications Public/Granted day:2007-12-13
Information query
IPC分类:
