Invention Grant
- Patent Title: Leaded stacked packages having integrated upper lead
- Patent Title (中): 具有集成上引线的带铅堆叠封装
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Application No.: US11459568Application Date: 2006-07-24
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Publication No.: US07667308B2Publication Date: 2010-02-23
- Inventor: Byung Tai Do , Francis Heap Hoe Kuan , Seng Guan Chow
- Applicant: Byung Tai Do , Francis Heap Hoe Kuan , Seng Guan Chow
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agent Robert D. Atkins
- Main IPC: H01L23/495
- IPC: H01L23/495

Abstract:
A semiconductor package includes a leadframe. An upper lead is disposed above the leadframe. A first die is attached to a lower surface of the upper lead to provide electrical conductivity from the first die to the upper lead. A second die is attached to the first die. A method of manufacturing a semiconductor package includes providing a leadframe having an upper lead, lower lead, and an elevated die paddle. A first die, attached to a plurality of dies in a wafer form, is attached to a second die. The first die is singulated from the plurality of dies. The first and second dies are attached to the elevated die paddle structure. The first die is wire bonded to the lower lead. An encapsulant is formed over the first and second dies. The elevated die paddle is removed to expose a surface of the upper lead and second die.
Public/Granted literature
- US20080017957A1 LEADED STACKED PACKAGES HAVING INTEGRATED UPPER LEAD Public/Granted day:2008-01-24
Information query
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