Invention Grant
- Patent Title: Fan out type wafer level package structure and method of the same
- Patent Title (中): 扇出式晶圆级封装结构及其方法
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Application No.: US12255868Application Date: 2008-10-22
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Publication No.: US07667318B2Publication Date: 2010-02-23
- Inventor: Wen-Kun Yang , Wen-Pin Yang , Shih-Li Chen
- Applicant: Wen-Kun Yang , Wen-Pin Yang , Shih-Li Chen
- Applicant Address: TW Hsinchu County
- Assignee: Advanced Chip Engineering Technology Inc.
- Current Assignee: Advanced Chip Engineering Technology Inc.
- Current Assignee Address: TW Hsinchu County
- Agency: Kusner & Jaffe
- Main IPC: H01L23/12
- IPC: H01L23/12 ; H01L23/053

Abstract:
To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.
Public/Granted literature
- US20090051025A1 FAN OUT TYPE WAFER LEVEL PACKAGE STRUCTURE AND METHOD OF THE SAME Public/Granted day:2009-02-26
Information query
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