Invention Grant
US07667497B2 Process variation tolerant circuit with voltage interpolation and variable latency
失效
具有电压内插和可变延迟的过程变差容限电路
- Patent Title: Process variation tolerant circuit with voltage interpolation and variable latency
- Patent Title (中): 具有电压内插和可变延迟的过程变差容限电路
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Application No.: US12261771Application Date: 2008-10-30
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Publication No.: US07667497B2Publication Date: 2010-02-23
- Inventor: Xiaoyao Liang , David Brooks , Gu-Yeon Wei
- Applicant: Xiaoyao Liang , David Brooks , Gu-Yeon Wei
- Applicant Address: US MA Cambridge
- Assignee: President and Fellows of Harvard College
- Current Assignee: President and Fellows of Harvard College
- Current Assignee Address: US MA Cambridge
- Agency: 24IP Law Group
- Agent Timothy R. DeWitt
- Main IPC: H03K19/00
- IPC: H03K19/00

Abstract:
A circuit having dynamically controllable power. The circuit comprises a plurality of pipelined stages, each of the pipelined stages comprising two clocking domains, a plurality of switching circuits, each switching circuit being connected to one of the pipelined stages, first and second power sources connected to each of the plurality of pipelined stages through the switching circuits, the first power source supplying a first voltage and the second power source supplying a second voltage, wherein the first and second power sources each may be applied to a pipelined stage independently of other pipelined stages, first and second complementary clocks, and a plurality of latches connected to the first and second complementary clocks and to the plurality of pipelined stages for proving latch-based clocking to control the first and second clocking domains and to enable time-borrowing across the plurality of switching circuits. The first voltage differs from the second voltage and the plurality of pipelined stages interpolates between the first and second voltages to provide differing effective voltages between the first and second voltages.
Public/Granted literature
- US20090134707A1 Process Variation Tolerant Circuit With Voltage Interpolation And Variable Latency Public/Granted day:2009-05-28
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