Invention Grant
- Patent Title: Edge-timing adjustment circuit
- Patent Title (中): 边沿定时调整电路
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Application No.: US12146663Application Date: 2008-06-26
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Publication No.: US07667507B2Publication Date: 2010-02-23
- Inventor: Mark L. Neidengard
- Applicant: Mark L. Neidengard
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Buckley, Maschoff & Talwalkar LLC
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
According to some embodiments, a method and system are provided to receive a clock input at a first clock adjustment tuner, receive the clock input at a second clock adjustment tuner, output a tuned inverted rising clock signal via the first clock adjustment tuner, output a tuned inverted falling clock signal via the second clock adjustment tuner, receive the inverted rising clock signal and the inverted falling clock signal at a clock synchronizer, output a synchronized tuned clock signal via the clock synchronizer, receive the synchronized tuned clock signal at a third clock adjustment tuner, and output a tuned clock signal. The first clock adjustment tuner and the second clock adjustment tuner provide coarser adjustments than the third clock adjustment tuner.
Public/Granted literature
- US20090322393A1 EDGE-TIMING ADJUSTMENT CIRCUIT Public/Granted day:2009-12-31
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