Invention Grant
US07667513B2 Digital duty cycle corrector 失效
数字占空比校正器

Digital duty cycle corrector
Abstract:
A circuit and method of correcting the duty cycle of digital signals is disclosed. The duty cycle of an input digital signal is measured and compared to a desired duty cycle. The leading edge of the input digital signal is passed to an output. The circuit and method adjust the falling edges at the output to achieve the desired duty cycle. The falling edges occur in response to rising edges of a delayed version of the input digital signal.
Public/Granted literature
Information query
Patent Agency Ranking
0/0