Invention Grant
US07667936B2 High-voltage tolerant power-rail ESD clamp circuit for mixed-voltage I/O interface
有权
用于混合电压I / O接口的高耐压电源轨ESD钳位电路
- Patent Title: High-voltage tolerant power-rail ESD clamp circuit for mixed-voltage I/O interface
- Patent Title (中): 用于混合电压I / O接口的高耐压电源轨ESD钳位电路
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Application No.: US12134061Application Date: 2008-06-05
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Publication No.: US07667936B2Publication Date: 2010-02-23
- Inventor: Ming-Dou Ker , Wen-Yi Chen , Che-Hao Chuang
- Applicant: Ming-Dou Ker , Wen-Yi Chen , Che-Hao Chuang
- Applicant Address: TW Hsinchu
- Assignee: Industrial Technology Research Institute
- Current Assignee: Industrial Technology Research Institute
- Current Assignee Address: TW Hsinchu
- Agency: Alston & Bird LLP
- Main IPC: H02H3/20
- IPC: H02H3/20 ; H02H3/22 ; H02H9/04

Abstract:
A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.
Public/Granted literature
- US20080232013A1 High-Voltage Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Interface Public/Granted day:2008-09-25
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