A circuit fault detector and interrupter which consists of parallel current conduction paths, including a path through a mechanical contactor and a path through a power electronics switch. A fault can be detected by a fault detection circuit within 50 microseconds of the occurrence of the fault, causing the mechanical contactor to be opened and the fault current to be commutated via a laminated, low-inductance bus through the power electronics switch. The power electronics switch is thereafter turned off as soon as possible, interrupting the fault current. The fault current can be interrupted within 200 microseconds of the occurrence of the fault, and the device reduces or eliminates arcing when the mechanical contactor is opened.