Invention Grant
US07667993B2 Dual-ported and-type match-line circuit for content-addressable memories
有权
用于内容寻址存储器的双端口和类型匹配线电路
- Patent Title: Dual-ported and-type match-line circuit for content-addressable memories
- Patent Title (中): 用于内容寻址存储器的双端口和类型匹配线电路
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Application No.: US11907524Application Date: 2007-10-12
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Publication No.: US07667993B2Publication Date: 2010-02-23
- Inventor: Chao-Ching Wang , Chieh-Jen Cheng , Jinn-Shyan Wang , Tien-Fu Chen
- Applicant: Chao-Ching Wang , Chieh-Jen Cheng , Jinn-Shyan Wang , Tien-Fu Chen
- Applicant Address: TW
- Assignee: National Chung Cheng University
- Current Assignee: National Chung Cheng University
- Current Assignee Address: TW
- Agency: Jackson IPG PLLC
- Main IPC: G11C15/00
- IPC: G11C15/00
Abstract:
A dual-ported AND-type match-line circuit includes at least one dual-ported dynamic AND gate. The dual-ported dynamic AND gate includes a group of CAM cells and a dual-ported dynamic circuit. A group of CAM cells connected to a dual-ported dynamic circuit and to the GND. The dual-ported dynamic circuit is connected to a group of CAM cells. The dual-ported dynamic circuit includes a setting circuit, a first directing circuit, a second directing circuit, a first AND dynamic output circuit and a second AND dynamic output circuit.
Public/Granted literature
- US20090097294A1 Dual-ported and-type match-line circuit for content-addressable memories Public/Granted day:2009-04-16
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