An input circuit of a semiconductor memory apparatus includes a first frequency control unit which receives a first signal and a second frequency control unit which receives a second signal. The first frequency control unit outputs the first signal to the second frequency control unit in response to a test mode signal and generates a third signal which has a frequency higher than the frequencies of the first and second signals by using the first and second signals. Also, the second frequency control unit outputs the second signal to the first frequency control unit in response to the test mode signal and generates a fourth signal which has a frequency higher than the frequencies of the first and second signals by using the first and second signals.