Invention Grant
US07669158B2 Method and system for semiconductor design hierarchy analysis and transformation 有权
半导体设计层次分析与转型的方法与系统

Method and system for semiconductor design hierarchy analysis and transformation
Abstract:
A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.
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