Invention Grant
- Patent Title: Method and system for semiconductor design hierarchy analysis and transformation
- Patent Title (中): 半导体设计层次分析与转型的方法与系统
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Application No.: US10955067Application Date: 2004-09-30
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Publication No.: US07669158B2Publication Date: 2010-02-23
- Inventor: Vishnu Govind Kamat
- Applicant: Vishnu Govind Kamat
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Sheppard Mullin Richter & Hampton LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.
Public/Granted literature
- US20060075371A1 Method and system for semiconductor design hierarchy analysis and transformation Public/Granted day:2006-04-06
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