Invention Grant
- Patent Title: Method of generating a layout for a differential circuit
- Patent Title (中): 生成差分电路布局的方法
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Application No.: US11764147Application Date: 2007-06-15
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Publication No.: US07669312B2Publication Date: 2010-03-02
- Inventor: Manolis Terrovitis
- Applicant: Manolis Terrovitis
- Applicant Address: US CA Santa Clara
- Assignee: Atheros Communications, Inc.
- Current Assignee: Atheros Communications, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Bever, Hoffman & Harms, LLP
- Agent Jeanette S. Harms
- Main IPC: H01F7/06
- IPC: H01F7/06

Abstract:
A differential circuit layout can advantageously use step symmetry for inductors and mirror symmetry for the rest of the circuit. Interconnect segments can be used to connect the terminals of the inductors to other components in the circuit. These interconnect segments facilitate the transition from the step symmetry of the inductors to the mirror symmetry of the other components. To provide this transition, the terminals of an inductor and its associated interconnect segments are formed on a middle axis of the inductor. This mixed symmetry can advantageously cancel the common-mode magnetic field, reduce the parasitic inductor coupling, and balance parasitic wiring capacitances between the two sides of the differential circuit.
Public/Granted literature
- US20070240298A1 Inductor Layout Using Step Symmetry For Inductors Public/Granted day:2007-10-18
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