Invention Grant
- Patent Title: Method for manufacturing vertical MOS transistor
- Patent Title (中): 垂直MOS晶体管的制造方法
-
Application No.: US12183093Application Date: 2008-07-31
-
Publication No.: US07670911B2Publication Date: 2010-03-02
- Inventor: Kiyonori Oyu
- Applicant: Kiyonori Oyu
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2007-208194 20070809
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method for manufacturing a vertical MOS transistor comprising forming a protrusion-like region, forming a silicon oxide film on an exposed surface of the protrusion-like region and a surface of the silicon semiconductor substrate, increasing a film thickness of at least the silicon oxide film on the silicon semiconductor substrate by thermal oxidation to form a first insulating film, forming a lower impurity diffusion region, removing the silicon oxide film to expose a silicon side of the protrusion-like region, thermally oxidizing the silicon side to form a second insulating film having a thinner film thickness than a film thickness of the first insulating film, forming a gate electrode over a side of the protrusion-like region, and forming an upper impurity diffusion region.
Public/Granted literature
- US20090042347A1 METHOD FOR MANUFACTURING VERTICAL MOS TRANSISTOR Public/Granted day:2009-02-12
Information query
IPC分类: