Invention Grant
- Patent Title: Methods for fabricating semiconductor structures with backside stress layers
- Patent Title (中): 制造具有背侧应力层的半导体结构的方法
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Application No.: US11748738Application Date: 2007-05-15
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Publication No.: US07670931B2Publication Date: 2010-03-02
- Inventor: Roey Shaviv
- Applicant: Roey Shaviv
- Applicant Address: US CA San Jose
- Assignee: Novellus Systems, Inc.
- Current Assignee: Novellus Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/322
- IPC: H01L21/322

Abstract:
Methods for fabricating semiconductor structures with backside stress layers are provided. In one exemplary embodiment, the method comprises the steps of providing a semiconductor device formed on and within a front surface of a semiconductor substrate. The semiconductor device comprises a channel region. A plurality of dielectric layers is formed overlying the semiconductor device. The plurality of dielectric layers comprises conductive connections that are in electrical communication with the semiconductor device. A backside stress layer is formed on a back surface of the semiconductor substrate. The backside stress layer is configured to apply to the channel region of the semiconductor device a uniaxial compressive or tensile stress that, with stresses applied by the plurality of dielectric layers, results in an overall stress exerted on the channel region to achieve a predetermined overall strain of the channel region.
Public/Granted literature
- US20080286918A1 Methods for Fabricating Semiconductor Structures With Backside Stress Layers Public/Granted day:2008-11-20
Information query
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