Invention Grant
- Patent Title: SOI device with reduced junction capacitance
- Patent Title (中): 具有降低结电容的SOI器件
-
Application No.: US11859865Application Date: 2007-09-24
-
Publication No.: US07671413B2Publication Date: 2010-03-02
- Inventor: Toshiharu Furukawa
- Applicant: Toshiharu Furukawa
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Schmeiser, Olsen & Watts
- Agent Richard M. Kotulak
- Main IPC: H01L29/76
- IPC: H01L29/76

Abstract:
An SOI FET comprising a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region is disclosed. The doped region has a dielectric constant different from the dielectric constant of the doped regions. A body also in the silicon layer separates the source/drains in the silicon layer. The source/drains are aligned over the doped regions and the body is aligned over the undoped region. A gate dielectric is on top of the body and a gate conductor is on top of the gate dielectric.
Public/Granted literature
- US20080006901A1 SOI DEVICE WITH REDUCED JUNCTION CAPACITANCE Public/Granted day:2008-01-10
Information query
IPC分类: