A memory cell array includes isolated semiconductor regions formed on a supporting insulating substrate, memory cells formed in the respective semiconductor regions, and insulating regions formed so as to insulate the memory cells. Each memory cell formed in a semiconductor region includes a source region, a drain region, a front gate region formed on a gate insulating film formed on one of side surfaces of the semiconductor region such that the source region and the drain region are separated from each other by the front gate region, and a back gate region formed on a gate insulating film formed on an opposite side surface of the semiconductor region such that the source region and the drain region are separated from each other by the back gate region. Each memory cell shares the back gate region with a memory cell adjacent in a row direction.