Invention Grant
- Patent Title: Buried via technology for three dimensional integrated circuits
- Patent Title (中): 埋在三维集成电路技术中
-
Application No.: US11624633Application Date: 2007-01-18
-
Publication No.: US07671460B2Publication Date: 2010-03-02
- Inventor: Stefan C. Lauxtermann , Jeffrey F. DeNatale
- Applicant: Stefan C. Lauxtermann , Jeffrey F. DeNatale
- Applicant Address: US CA Thousand Oaks
- Assignee: Teledyne Licensing, LLC
- Current Assignee: Teledyne Licensing, LLC
- Current Assignee Address: US CA Thousand Oaks
- Agency: Snell & Wilmer L.L.P.
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
A three dimensional integrated circuit and method for making the same. The three dimensional integrated circuit has a first and a second active circuit layers with a first metal layer and a second metal layer, respectively. The metal layers are connected by metal inside a buried via. The fabrication method includes etching a via in the first active circuit layer to expose the first metal layer without penetrating the first metal layer, depositing metal inside the via, the metal inside the via being in contact with the first metal layer, and bonding the second active circuit layer to the first active circuit layer using a metal bond that connects the metal inside the via to the second metal layer of the second active circuit layer.
Public/Granted literature
- US20070170574A1 BURIED VIA TECHNOLOGY FOR THREE DIMENSIONAL INTEGRATED CIRCUITS Public/Granted day:2007-07-26
Information query
IPC分类: