A PWM modulator adds first and second input signals to each other, and performs PWM modulation processing for outputting a PWM-modulated pulse whose pulse width is modulated according to a result of addition. A shift register delays a bit stream acquired from a ΔΣ modulator, thereby generating two bit streams having a time difference which is one-half a period of PWM modulation processing, and the bit streams are supplied at first and second input signals to the PWM modulator.