Invention Grant
- Patent Title: FET bias circuit
- Patent Title (中): FET偏置电路
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Application No.: US11994702Application Date: 2005-07-05
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Publication No.: US07671684B2Publication Date: 2010-03-02
- Inventor: Tamaki Honda , Hironori Sakamoto , Kenjiro Okadome
- Applicant: Tamaki Honda , Hironori Sakamoto , Kenjiro Okadome
- Applicant Address: JP
- Assignee: Japan Radio Co., Ltd.
- Current Assignee: Japan Radio Co., Ltd.
- Current Assignee Address: JP
- Agency: Cantor Colburn LLP
- Priority: JP2005-196492 20050705
- International Application: PCT/JP2006/313404 WO 20050705
- International Announcement: WO2007/004673 WO 20071101
- Main IPC: H03F3/04
- IPC: H03F3/04

Abstract:
A FET bias circuit applies a bias voltage that is not adjusted separately to an amplifying element FET of a FET amplifying circuit. In the FET bias circuit is provided a monitor element FET m having a gate connected to the gate of the amplifying element FET a and a source connected to the source of the amplifying element FET a, respectively, and having a drain current with respect to the bias voltage substantially proportional to the drain current of the amplifying element FET a. In the FET bias circuit is further provided a fixed bias circuit for applying the bias voltage so that the amplifying element FET a enters a predetermined operating class by applying a bias voltage to the monitor element FET m so that a drain current flowing to the monitor element FET m enters a predetermined operating class.
Public/Granted literature
- US20090115526A1 FET BIAS CIRCUIT Public/Granted day:2009-05-07
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