Parallel data bus architecture, lithography system and method for substrate patterning with a high-resolution image by data generation transferring, display or printing high edge placement accuracy images from multiple exposures of plurality of predefined patterns with lower edge placement accuracy. Data bus architecture includes n predetermined patterns in n memory arrays each storing a low resolution pattern to be formed onto microelement array with a data bus connecting memory arrays to an image transducer memory array. Data bus includes switches allowing data transfer from any one memory array to the image transducer array with a memory control unit connected to memory arrays and one or more data bus switches so 2m−1 columns of pattern data stored in the mth memory array are sequentially transferred to 2m−1 memory cell columns of the image transducer memory array, m an integer begging at 1 incremented by 1 to n.