Invention Grant
- Patent Title: Non-planar flash memory array with shielded floating gates on silicon mesas
- Patent Title (中): 具有屏蔽浮栅的非平面闪存阵列
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Application No.: US12013598Application Date: 2008-01-14
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Publication No.: US07672171B2Publication Date: 2010-03-02
- Inventor: Leonard Forbes , Kie Y. Ahn
- Applicant: Leonard Forbes , Kie Y. Ahn
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Main IPC: G11C16/06
- IPC: G11C16/06
Abstract:
A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of memory cells is coupled to the first plurality of memory cells through a series connection of their source/drain regions. Wordlines couple rows of memory cells of the array. Metal shields are formed between adjacent wordlines and substantially parallel to the wordlines to shield the floating gates of adjacent cells.
Public/Granted literature
- US20080112228A1 NON-PLANAR FLASH MEMORY ARRAY WITH SHIELDED FLOATING GATES ON SILICON MESAS Public/Granted day:2008-05-15
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