Invention Grant
US07672173B2 Non-volatile semiconductor memory device and semiconductor memory device 有权
非易失性半导体存储器件和半导体存储器件

Non-volatile semiconductor memory device and semiconductor memory device
Abstract:
For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are reset to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.
Information query
Patent Agency Ranking
0/0