A semiconductor memory device includes an address buffer, a row decoder, a column decoder, a fuse circuit, a memory cell array including regular and redundant memory cells, a regulator, a regular sense amplifier, a redundant sense amplifier, a selection circuit, an input/output buffer, and a test control circuit for a test mode. The test control circuit controls the regular and redundant sense amplifiers so as to output the signal upon accessing a regular memory cell different in level from that output upon accessing a redundant memory cell, whereby a failed address can be electrically confirmed with ease.