Invention Grant
- Patent Title: Digital predistorter and predistortion method therefor
- Patent Title (中): 数字预失真器和预失真方法
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Application No.: US11247267Application Date: 2005-10-12
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Publication No.: US07672395B2Publication Date: 2010-03-02
- Inventor: Shinji Mizuta , Yasunori Suzuki , Shoichi Narahashi
- Applicant: Shinji Mizuta , Yasunori Suzuki , Shoichi Narahashi
- Applicant Address: JP Tokyo
- Assignee: NTT DoCoMo, Inc.
- Current Assignee: NTT DoCoMo, Inc.
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2004-312620 20041027
- Main IPC: H04L25/49
- IPC: H04L25/49

Abstract:
A predistorter includes: a divider that divides an input signal and supplies the divided input signal to a linear transmission path and a distortion generating path; a (2k−1)th-order distortion generator that raises the signal supplied to the distortion generating path to the (2k−1)th power to generate a distortion component; a vector adjuster that adjusts the amplitude and phase of the output of the (2k−1)th-order distortion generator; and an adder that sums up the output of the vector adjuster and the output of the linear transmission path to generate a predistorted signal r(t), in which the (2k−1)th-order distortion generator comprises: a (2k−1)th-order multiplier (27B4) that raises the divided signal to the (2k−1)th power; a lower-than-(2k−1)th-order multiplier (27B3, 27B2, 27B1) that raises the divided signal to the 5th, 3rd and 1st power, respectively; a vector adjuster (27C3, 27C2, 27C1) that adjusts the amplitude and phase of the output of the lower-than-(2k−1)th-order multiplier; and an adder (27D) that sums up the output of the vector adjuster and the output of the (2k−1)th-order multiplier.
Public/Granted literature
- US20060088124A1 Digital predistorter and predistortion method therefor Public/Granted day:2006-04-27
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