Invention Grant
US07673091B2 Method to hide or reduce access latency of a slow peripheral in a pipelined direct memory access system
有权
在流水线直接存储器访问系统中隐藏或减少慢外设的访问延迟的方法
- Patent Title: Method to hide or reduce access latency of a slow peripheral in a pipelined direct memory access system
- Patent Title (中): 在流水线直接存储器访问系统中隐藏或减少慢外设的访问延迟的方法
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Application No.: US12107274Application Date: 2008-04-22
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Publication No.: US07673091B2Publication Date: 2010-03-02
- Inventor: Ashutosh Tiwari , Subrangshu Kumar Das
- Applicant: Ashutosh Tiwari , Subrangshu Kumar Das
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Priority: IN866/CHE/2007 20070424
- Main IPC: G06F13/00
- IPC: G06F13/00
Abstract:
A bus bridge between a high speed DMA bus and a lower speed peripheral bus sets a threshold for minimum available buffer space to send a read request dependent upon a frequency ratio and the DMA read latency. Similarly, a threshold for minimum available data for a write request depends on the frequency ratio and the DMA write latency. The bus bridge can store programmable values for the DMA read latency and write latency.
Public/Granted literature
- US20080270668A1 Method to Hide or Reduce Access Latency of a Slow Peripheral in a Pipelined Direct Memory Access System Public/Granted day:2008-10-30
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