Invention Grant
US07673200B2 Reprogrammable built-in-self-test integrated circuit and test method for the same
失效
可重复编程的内置自检集成电路和测试方法相同
- Patent Title: Reprogrammable built-in-self-test integrated circuit and test method for the same
- Patent Title (中): 可重复编程的内置自检集成电路和测试方法相同
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Application No.: US11870242Application Date: 2007-10-10
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Publication No.: US07673200B2Publication Date: 2010-03-02
- Inventor: Hsun-Yao Jan , Ting-Han Su , Cheng-Fang Yang
- Applicant: Hsun-Yao Jan , Ting-Han Su , Cheng-Fang Yang
- Applicant Address: TW Hsinchu
- Assignee: Asix Electronics Corporation
- Current Assignee: Asix Electronics Corporation
- Current Assignee Address: TW Hsinchu
- Agency: Sinorica, LLC
- Agent Ming Chow
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
The present invention discloses a reprogrammable built-in-self-test integrated circuit and a test method for the same, wherein test programs are directly stored in the application program memory of the logic chip of a SoC IC, and an external test apparatus is used to load the test programs into the application program memory via a serial transmission interface, and an application CPU is used to read and execute the test programs to perform the bonding-wire connectivity between the logic chip and the memory chip. In the present invention, test vectors can still be flexibly revised after tapeout to increase test coverage. As the test programs are directly stored in the existing application program memory without using additional memory space, and as the test programs are executed by the existing application CPU without using an extra built-in-self-test circuit, the present invention can effectively reduce test cost.
Public/Granted literature
- US20090100305A1 REPROGRAMMABLE BUILT-IN-SELF-TEST INTEGRATED CIRCUIT AND TEST METHOD FOR THE SAME Public/Granted day:2009-04-16
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