Invention Grant
- Patent Title: Method and system for conducting a low-power design exploration
- Patent Title (中): 进行低功率设计勘探的方法和系统
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Application No.: US11588927Application Date: 2006-10-26
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Publication No.: US07673276B2Publication Date: 2010-03-02
- Inventor: Qi Wang
- Applicant: Qi Wang
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Duane Morris LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Method and system for conducting low-power design explorations are disclosed. The method includes receiving an RTL netlist of a circuit design, creating one or more power requirement files, wherein each power requirement file comprises power commands corresponding to the RTL netlist, generating one or more low-power RTL netlists using the corresponding one or more power requirement files and the RTL netlist, and conducting low-power design explorations using the one or more low-power RTL netlists.
Public/Granted literature
- US20080126999A1 Method and system for conducting a low-power design exploration Public/Granted day:2008-05-29
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