Invention Grant
US07674637B2 Monitoring cool-down stress in a flip chip process using monitor solder bump structures
失效
在使用监测焊料凸点结构的倒装芯片工艺中监控冷却应力
- Patent Title: Monitoring cool-down stress in a flip chip process using monitor solder bump structures
- Patent Title (中): 在使用监测焊料凸点结构的倒装芯片工艺中监控冷却应力
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Application No.: US11749885Application Date: 2007-05-17
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Publication No.: US07674637B2Publication Date: 2010-03-09
- Inventor: Charles F. Carey , Bernt Julius Hansen , Ashwani K. Malhotra , David L. Questad , Wolfgang Sauter
- Applicant: Charles F. Carey , Bernt Julius Hansen , Ashwani K. Malhotra , David L. Questad , Wolfgang Sauter
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Schmeiser, Olsen & Watts
- Agent Richard M. Kotulak
- Main IPC: G01L31/26
- IPC: G01L31/26 ; H01L21/66

Abstract:
A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.
Public/Granted literature
- US20080286886A1 Monitoring Cool-Down Stress in a Flip Chip Process Using Monitor Solder Bump Structures Public/Granted day:2008-11-20
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