Invention Grant
- Patent Title: Semiconductor device isolation structures and methods of fabricating such structures
- Patent Title (中): 半导体器件隔离结构及其制造方法
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Application No.: US11654588Application Date: 2007-01-18
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Publication No.: US07674685B2Publication Date: 2010-03-09
- Inventor: Jong-Wan Choi , Ju-Seon Goo , Hong-Gun Kim , Yong-Soon Choi , Sung-Tae Kim , Eun-Kyung Baek
- Applicant: Jong-Wan Choi , Ju-Seon Goo , Hong-Gun Kim , Yong-Soon Choi , Sung-Tae Kim , Eun-Kyung Baek
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co, Ltd.
- Current Assignee: Samsung Electronics Co, Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2006-0065531 20060712
- Main IPC: H01L21/76
- IPC: H01L21/76

Abstract:
Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.
Public/Granted literature
- US20080014711A1 Semiconductor device isolation structures and methods of fabricating such structures Public/Granted day:2008-01-17
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