Methods of forming interconnections for an electronic device including a substrate may be provided. For example, first and second patterned layers may be formed on the substrate wherein an opening in the first and second patterned layers exposes portions of the substrate, wherein the first and second patterned layers have different compositions, and wherein the first patterned layer is between the second patterned layer and the substrate. A metal layer may be formed on the second patterned layer and on portions of the substrate exposed through the opening in the first and second patterned layers. The second patterned layer and portions of the metal layer thereon may be removed while maintaining portions of the metal layer on the portions of the substrate exposed through the opening. After removing the second mask layer, solder may be provided on the metal layer.