Invention Grant
US07675179B2 Device and method to eliminate shorting induced by via to metal misalignment
有权
消除由通孔到金属不对准引起的短路的装置和方法
- Patent Title: Device and method to eliminate shorting induced by via to metal misalignment
- Patent Title (中): 消除由通孔到金属不对准引起的短路的装置和方法
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Application No.: US11738050Application Date: 2007-04-20
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Publication No.: US07675179B2Publication Date: 2010-03-09
- Inventor: Ranbir Singh , Sen Sidhartha , Nace Rossi
- Applicant: Ranbir Singh , Sen Sidhartha , Nace Rossi
- Applicant Address: US PA Allentown
- Assignee: Agere Systems Inc.
- Current Assignee: Agere Systems Inc.
- Current Assignee Address: US PA Allentown
- Main IPC: H01L23/522
- IPC: H01L23/522

Abstract:
The present invention provides an interconnect that can be employed in an integrated circuit. The interconnect includes a metal line located over a substrate, a dielectric layer located over the metal line, and an interconnect located in the dielectric layer, including a landed portion located over the metal line and an unlanded portion located along at least a portion of a lateral edge of the metal line. The unlanded portion is at least partially filled with a polymer, and the landed portion is substantially filled with a conductive material. A method for manufacturing the interconnect is also provided.
Public/Granted literature
- US20070190803A1 DEVICE AND METHOD TO ELIMINATE SHORTING INDUCED BY VIA TO METAL MISALIGNMENT Public/Granted day:2007-08-16
Information query
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