Invention Grant
US07675784B2 Semiconductor memory device with dummy bit lines for charge and discharge timing
有权
具有用于充电和放电定时的虚拟位线的半导体存储器件
- Patent Title: Semiconductor memory device with dummy bit lines for charge and discharge timing
- Patent Title (中): 具有用于充电和放电定时的虚拟位线的半导体存储器件
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Application No.: US11948715Application Date: 2007-11-30
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Publication No.: US07675784B2Publication Date: 2010-03-09
- Inventor: Yoshinobu Kaneda
- Applicant: Yoshinobu Kaneda
- Applicant Address: JP Osaka JP Gunma
- Assignee: Sanyo Electric Co., Ltd.,Sanyo Semiconductor Co., Ltd.
- Current Assignee: Sanyo Electric Co., Ltd.,Sanyo Semiconductor Co., Ltd.
- Current Assignee Address: JP Osaka JP Gunma
- Agency: Morrison & Foerster LLP
- Priority: JP2006-323023 20061130
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/06

Abstract:
The invention provides a semiconductor memory device which realizes high speed reading by automatically adjusting and optimizing charge and discharge timings even when a change in an operation environment such as a variation in an operation voltage, an operation temperature, a process parameter and so on occurs. First and second dummy bit lines are provided for a bit line, each having a wiring load twice the wiring load of the bit line. A first sense circuit sensing the voltage of the first dummy bit line is provided to control a charging time according to a first sense signal. A second sense circuit sensing the voltage of the second dummy bit line is further provided to control a discharging time according to a second sense signal. A sense amplifier sensing the voltage of the bit line is activated in response to the second sense signal.
Public/Granted literature
- US20080130369A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2008-06-05
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