A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes a read command buffer to provide the read signal. The latency circuit receives the read signal, and provides a latency signal having a difference of a predetermined time corresponding to CAS latency with respect to the read signal in response to the transfer signal.