Invention Grant
US07675924B2 Gigabit switch on chip architecture 有权
千兆开关芯片架构

Gigabit switch on chip architecture
Abstract:
A data switch for network communications includes a first data port interface and a second data port interface is provided supporting at least one data port transmitting and receiving data. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. A common memory is provided, and communicates with the first data port interface and the second data port interface. A memory management unit is provided, and communicates data from the first data port interface and the second data port interface and a common memory. At least two sets of communication channels are provided, with each of the communication channels communicating data and messaging information between the first data port interface, the second data port interface, and the memory management unit.
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