Invention Grant
US07675930B2 Chip circuit for combined and data compressed FIFO arbitration for a non-blocking switch
失效
用于非阻塞开关的组合和数据压缩FIFO仲裁的片状电路
- Patent Title: Chip circuit for combined and data compressed FIFO arbitration for a non-blocking switch
- Patent Title (中): 用于非阻塞开关的组合和数据压缩FIFO仲裁的片状电路
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Application No.: US12033867Application Date: 2008-02-19
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Publication No.: US07675930B2Publication Date: 2010-03-09
- Inventor: Francois Abel , Gottfried Andreas Goldrian , Ingemar Holm , Helmut Kohler , Norbert Schumacher
- Applicant: Francois Abel , Gottfried Andreas Goldrian , Ingemar Holm , Helmut Kohler , Norbert Schumacher
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporaiton
- Current Assignee: International Business Machines Corporaiton
- Current Assignee Address: US NY Armonk
- Agent Floyd A. Gonzalez; John E. Campbell
- Priority: EP02009571 20020426
- Main IPC: H04L12/54
- IPC: H04L12/54
Abstract:
A system for switching data packets through a multiple (m) input, multiple (n) output switching device providing switching having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.
Public/Granted literature
- US20080212577A1 CHIP CIRCUIT FOR COMBINED AND DATA COMPRESSED FIFO ARBITRATION FOR A NON-BLOCKING SWITCH Public/Granted day:2008-09-04
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