Invention Grant
- Patent Title: Fail-silent node architecture
- Patent Title (中): 故障静默节点架构
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Application No.: US11303563Application Date: 2005-12-16
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Publication No.: US07676286B2Publication Date: 2010-03-09
- Inventor: Robert J. Disser , Paul M. Degoul , Steven L. Tracht
- Applicant: Robert J. Disser , Paul M. Degoul , Steven L. Tracht
- Agency: Dickinson Wright PLLC
- Main IPC: G05B15/00
- IPC: G05B15/00 ; G06F7/00 ; G06F11/00

Abstract:
A system including a node, wherein the node includes two separate controllers, each of which is configured to output data to a bus, or receive data from a bus, or output data to and receive data from a bus. At least one controller is configured to monitor the output of the other controller and is configured such that if the at least one controller determines that the other controller is providing improper data or signals, at least part of the output data of the other controller is nullified, overridden or superseded by an output from the at least one controller.
Public/Granted literature
- US20060162986A1 Fail-silent node architecture Public/Granted day:2006-07-27
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