The data interface device accesses a memory operating in synchronization with a clock. A board clock and selective data capturing improve the operating rate of a memory interface and time-synchronize data flow from memory to memory controller with a internal clock produced by the memory controller; or time-synchronize data flow from the memory controller with the board clock. The internal clock is passed through a sequential path of an output pad of the memory controller, the memory, and an input pad of the memory controller and then re-inputted into the memory controller thereby the feedback clock is generated. The selective data capturing uses a register part for storing data inputted into the memory controller. The register part for storing the data is configured by double registers that are operated in an alternative manner according to a correlation between the inputted data and the feedback clock.