Invention Grant
- Patent Title: Using a delay line to cancel clock insertion delays
- Patent Title (中): 使用延迟线来取消时钟插入延迟
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Application No.: US11383300Application Date: 2006-05-15
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Publication No.: US07676697B2Publication Date: 2010-03-09
- Inventor: Gary L. Swoboda
- Applicant: Gary L. Swoboda
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G06F11/00
- IPC: G06F11/00
Abstract:
A programmable delay is added to the data and clock data paths in order to cancel the effect of the clock insertion delays. This programmable delay is adjusted dynamically at runtime to optimize the performance of the interface.
Public/Granted literature
- US20060259821A1 Using a Delay Line to Cancel Clock Insertion Delays Public/Granted day:2006-11-16
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