Invention Grant
US07676712B2 System and method of clocking an IP core during a debugging operation
有权
在调试操作期间对IP核进行计时的系统和方法
- Patent Title: System and method of clocking an IP core during a debugging operation
- Patent Title (中): 在调试操作期间对IP核进行计时的系统和方法
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Application No.: US10501461Application Date: 2002-01-18
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Publication No.: US07676712B2Publication Date: 2010-03-09
- Inventor: Greg Bensinger , Jean-Marc Brault , Hans Erich Multhaup
- Applicant: Greg Bensinger , Jean-Marc Brault , Hans Erich Multhaup
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Agency: Banner & Witcoff, Ltd
- International Application: PCT/EP02/00503 WO 20020118
- International Announcement: WO03/060719 WO 20030724
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G06F11/00
Abstract:
According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock oscillator or any other free-running clock source.
Public/Granted literature
- US20060059388A1 System and method of clocking an ip core during a debugging operation Public/Granted day:2006-03-16
Information query
