A first FF outputs a first signal. A second FF captures the first signal and outputs a second signal. Each of the first and the second FF has a clock terminal to capture a clock signal. A third FF captures the first signal in parallel with the second FF. The third FF has a clock terminal to capture the clock signal in parallel with the clock terminal of the second FF. A buffer delays arrival of the clock signal to the clock terminal of the third FF. A comparing circuit compares the second signal and the third signal. An error collecting circuit captures a result of comparison to judge whether a timing error occurs in the second FF.