The programmable decoder, such as a Maximum Likelihood Sequence Estimation (MLSE) decoder (e.g. a Viterbi decoder) may include a programming input for a plurality of programmable trellis parameters, and a programmable device, such as an FPGA, connected to the programming input and implementing a continuous phase modulation (CPM) decoder including at least one trellis structure defined based upon the plurality of programmable trellis parameters. The plurality of programmable trellis parameters may include a number of trellis structures, a number of trellis states for each trellis structure, and a number of branches for each trellis state. Also, the trellis structure may include a reverse-state trellis structure.