Invention Grant
US07676774B2 System LSI verification system and system LSI verification method
失效
系统LSI验证系统和系统LSI验证方法
- Patent Title: System LSI verification system and system LSI verification method
- Patent Title (中): 系统LSI验证系统和系统LSI验证方法
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Application No.: US11749468Application Date: 2007-05-16
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Publication No.: US07676774B2Publication Date: 2010-03-09
- Inventor: Tomoko Kitazawa
- Applicant: Tomoko Kitazawa
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2006-137771 20060517
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/45

Abstract:
According to one embodiment, a system LSI verification system that verifies a processor module included in a system LSI, the system comprising: a circuit description storage that stores description data that describes a design of the processor module; a verification task generator that generates a verification task file based on the description data and a verification environment specification file in which specifications of a verification environment are described; a test program storage that stores a test program including an environment command function for starting the verification task; and a logical simulator that performs a logical simulation according to the test program.
Public/Granted literature
- US20070271533A1 SYSTEM LSI VERIFICATION SYSTEM AND SYSTEM LSI VERIFICATION METHOD Public/Granted day:2007-11-22
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